verilog HDLBits刷题[Finite State Machines]“Fsm ps2data”---PS/2 packet parser and datapath

1、题目See also: PS/2 packet parser.Now that you have a state machine that will identify three-byte messages in a PS/2 byte stream, add a datapath that will also output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.).out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., dont-care).For example:2、分析三个字节也就是24bit输出一次并拉高done。并且第一个字节的bit[3]一定是1。3、正确代码module top_module( input clk, input [7:0] in, input reset, // Synchronous reset output reg[23:0] out_bytes, output done); // parameter IDEL4d0001,BYTE14d0010,BYTE24d0100,BYTE34d1000; reg [3:0]state,next_state; always(*)begin case(state) IDEL: next_statein[3]?BYTE1:IDEL; BYTE1: next_stateBYTE2; BYTE2: next_stateBYTE3; BYTE3: next_statein[3]?BYTE1:IDEL; default:next_stateIDEL; endcase end always(posedge clk)begin if(reset) stateIDEL; else statenext_state; end always(posedge clk)begin if(reset) out_bytes24d0; else out_bytesout_bytes8|in;//左移8位低八位补0或上in end assign done(stateBYTE3); endmodule3-1、错误代码不知道为什么会这样module top_module( input clk, input [7:0] in, input reset, // Synchronous reset output [23:0] out_bytes, output done); // parameter IDEL4d0001,BYTE14d0010,BYTE24d0100,BYTE34d1000; reg [7:0]in_byte1,in_byte2,in_byte3; reg [3:0]state,next_state; always(*)begin case(state) IDEL:begin next_statein[3]?BYTE1:IDEL;in_byte1in;end BYTE1:begin next_stateBYTE2;in_byte2in;end BYTE2:begin next_stateBYTE3;in_byte3in;end BYTE3:begin next_statein[3]?BYTE1:IDEL;end default:next_stateIDEL; endcase end always(posedge clk)begin if(reset) stateIDEL; else statenext_state; end assign done(stateBYTE3); assign out_bytes(done)?{in_byte1,in_byte2,in_byte3}:24d0; endmodule4-1错误结果