制作 system.bit.bin创建 download.bifall:{system_wrapper.bit}PS D:\vitis_prj\system_wrapper$env:PATHD:\Xilinx\Vivado\2020.2\bin;$env:PATHPS D:\vitis_prj\system_wrapperbootgen-imagedownload.bif-archzynq-process_bitstreambin在板子上更新bit流cd/lib/firmware/echosystem_wrapper.bit.bin/sys/class/fpga_manager/fpga0/firmware配置自动登陆板子cat ~/.ssh/id_rsa.pub | ssh root192.168.1.102 mkdir -p ~/.ssh cat ~/.ssh/authorized_keys chmod 700 ~/.ssh chmod 600 ~/.ssh/authorized_keys自动脚本download.batecho off setlocal REMREM 用户配置 REMsetVITIS_BIND:\Xilinx\Vitis\2020.2\binsetSCPC:\Windows\System32\OpenSSH\scp.exesetSSHC:\Windows\System32\OpenSSH\ssh.exesetUSERrootsetIP192.168.1.102setREMOTE_DIR/lib/firmware/ REM 工程目录setRUN_DIRD:\workspace\gitee\ant_prj\ant_vivado\ant.runs\impl_1 REM 顶层名称setTOPsystem_wrapper REMcd/d %RUN_DIR% echo.echoGenerate bit.binifexist %TOP%.bit.bin del /f /q %TOP%.bit.bin(echoall:echo{echo%TOP%.bitecho})download.bif call%VITIS_BIN%\bootgen.bat^-imagedownload.bif ^-archzynq ^-process_bitstreambin ^-woniferrorlevel1goto error echo.echoUpload%SCP% %TOP%.bit.bin %USER%%IP%:%REMOTE_DIR%iferrorlevel1goto error echo.echoProgram FPGA%SSH% %USER%%IP%cd /lib/firmware/ echo %TOP%.bit.bin /sys/class/fpga_manager/fpga0/firmwareiferrorlevel1goto error echo.echoechoFPGA Download Success!echopauseexit/b0:error echo.echo*************************************echoFPGA Download Failed!echo************************************* pauseexit/b1